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FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
sa1117_fifo
- 3个模块：图像数据采集控制(12C总线)、FIFO读写控制器、与PCI接口芯片通信。- Three modules: image data acquisition and control (12C bus), FIFO read and write controller, and PCI interface chip communication.
sa1117_fifo_pic
- 3个模块：图像数据采集控制(12C总线)、FIFO读写控制器、与PCI接口芯片通信。- Three modules: image data acquisition and control (12C bus), FIFO read and write controller, and PCI interface chip communication.
CY7C68013-Slave-Control(2012-10-28)
- cy7c68013 Slave FIFO模式下的控制程序，和Agilent34401A积分信号发生状态机-failed to translate