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mips_project
- 我用verilog写的risc指令集的mips的cpu。可以支持定点运算。顶层单元是top。-I used to write verilog mips risc instruction set of the cpu. To support fixed-point arithmetic. Top-level unit is the top.
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
risc
- 基于quartus II软件 用verilog 语言描述的精简指令CPU-quartus II verilog
S7_PS2_RS232
- 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
CPU
- verilog 实现的CPU，用Modelsim SE 6.2b 创建的工程，包含测试文件。- CPU of verilog implementation
cpu8
- 用Verilog仿真8条基本指令的CPU，是学习编写多条指令CPU的基础-Verilog simulation with the basic instructions 8 CPU, CPU to learn the basis for the preparation of multiple instructions
Tomasulo2
- 用verilog编写流水CPU。采用Tomasulo算法，进一步的减少了等式右边的各项暂停时间，并通过阅读文献，实现了一种基于此算法原理的机器PowerPC 620的CPU的雏形-Tomasulo Based Speculative Processor
mp2
- 用verilog 写的微程序多周期CPU.软件版本为10.1-Micro-program written in verilog. Multi-cycle CPU software version 10.1
single-clock-CPU
- 单时钟周期CPU，verilog语言编写，quartusII运行-A single clock cycle CPU
CPU
- 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
pipelined-CPU
- verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
avr8_latest.tar
- AVR8 cpu的verilog 源码 欢迎下载使用 AVR8 cpu的verilog 源码 欢迎下载使用-AVR8 cpu s verilog welcome to download source code verilog using AVR8 cpu s welcome to download AVR8 cpu welcome to download the source code verilog
lab07
- 利用verilog语言编写一个单周期cpu实现加减乘除等十六条基本指令，模拟仿真通过。-Use verilog language to achieve a single cycle of addition, subtraction, etc. cpu sixteen basic instructions, simulation pass.
proc_pipe
- A 5 stage pipeline CPU written in verilog codes
88RISC-CPU
- cpu设计能在quartus上运行 用verilog语言-a cpu program use verilog on quartus
DLX_verilog
- DLX指令集RISC CPU verilog源码，使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
SensorHubDesignFilesSourceCode
- sensor-hub技术是最新出来的技术，目前用在智能手机领域，手机里面的传感器越来越多，这给CPU带来很大的负担，功耗也随之提高。sensor-hub技术出来后，可以有效的解决这个问题，这是运行在lattice FPGA平台上的verilog源代码，欢迎大家一起交流学习，希望能给你带来帮助。-Sensor- the hub is the latest technology, the current use in the field of smart phones, mobile phone i
MIPSCPUverilog
- mips流水线CPU的实现，用的是verilog语言，描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
cpu_verilog
- cpu的verilog描述的代码。比较适合初学者，-cpu verilog descr iption of the code. More suitable for beginners,
CPU
- 语言为verilog，平台是ISE，指令较少。32位MIPScpu，可以直接运行(The language is Verilog, the platform is ISE, and the instructions are fewer. 32 bit MIPScpu, can run directly)