搜索资源列表
verilog
- verilog分频程序，适合初学者，任意分频！-divider verilog procedures, suitable for beginners, arbitrary frequency!
8253TIMER
- 8253定时器实现分频，1秒定时子程序调用-8253 timer, divider, one second timer subroutine call
fenpin
- fpga的分频器，占空比为50 ，输出方波，同步脉冲-fpga divider, 50 duty cycle, the output square wave, the sync pulse
tongxinzongheshiyan
- 微波实验设计，设计波导滤波器和波导等功率分配器-Microwave experimental design, waveguide filter design and waveguide power divider etc.
clkNdiv
- 很经典的时钟分频代码，直接拿来可以使用 使用VHDL语言编写！-Very classic clock divider code can be directly used to use using VHDL language!
Alfc
- fdiv1.v 为异步加载分频电路设计源程序 fdiv1_sti.v 为仿真测试测试程序。 总的能实现电路设计EDA异步加载分频电路的设计并实现仿真。-fdiv1.v asynchronous load divider circuit design source fdiv1_sti.v for the simulation test program.
div
- vhdl除法器 vhdl除法器 vhdl除法器 -divider vhdl vhdl vhdl divider divider divider vhdl vhdl vhdl divider divider
vfxc
- 一种实用的除法器,对于初学者很大帮助，代码不大，精简好用。-A practical divider, very helpful for beginners, the code is not streamlined easy to use.
traffic
- 基于Verilog的交通灯，包含分频器模块、计数模块以及控制模块。状态机编写-Verilog-based traffic lights, including the divider block, counting module and a control module. Write state machine
firstTry
- pscad简单分压模型。包含电压表和电流表，实时显示波形-pscad simple voltage divider models. Includes voltmeter and ammeter, real-time waveform display
Binary_Divider_VHDL.txt.tar
- Code for a binary divider state machine.
DivFrec
- Employ IP cores in VHDL to describe some functions Module digital clock manager , in this case to create a frequency divider
shuzizhong
- 秒计数器，分计数器，时计数器，分频器，数字钟实验-Second counter, minute counter, counter, divider, digital clock experiment
ex1_clkdiv
- Verilog语言编写，通过此代码控制CPLD输出任意偶数倍分频-Verilog language, through this code control CPLD any even multiple output divider
lab
- ADS tool used to design wilkinson power divider
chapter9
- divider scl,d cfe lc,em l cme lrcm l ec lmrktn krnkelnl rlknecrlk clenrclke lkrclke lrenclek nkerncl lknrclke lkrencelrk lkcne ncrlekcnelk nlkercnlek-divider scl,d cfe lc,em l cme lrcm l ec lmrktn krnkelnl rlknecrlk clenrclke lkrclke lrenclek nker
frequency-divider
- 利用FPGA实现分频器功能并完成LED数码管静态和动态显示-Using FPGA to achieve crossover features and complete LED digital control static and dynamic display
diviseur
- it s descr iption in VHDL code of divider. this is complex arithmetic operation
streamline_div
- 一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
fenpinqi
- 基于vhdl语言编写的分频器程序，可实现五十分频。-Based divider vhdl language program, can achieve five very frequently.