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cntr_4bit
- This the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit-This is the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit
compare
- 八位字节比较器，四选一多路选择器，二分频电路-Octet comparator 4 election more than one way selector, the second divider circuit
fenpin
- 通用整数分频器，可以分频占空比为1:1，也可以为任意占空比-General integer frequency divider, can divide frequency and duty ratio of 1:1, also can be for any duty ratio
pulse8
- 任意占空比的8分频电路,也可以任意分频，经过优化，很稳定-Arbitrary duty 8 divider circuit may be arbitrarily divided optimized, very stable
divider8
- 使用硬件描述语言设计8分频器，并将结果通过七段数码管显示-The hardware descr iption language is used to design the 8-frequency divider, and the result is displayed by 7-segment LED
fenpin
- 分频器程序，可以进行分频，精度高，很不错！-Divider program can be frequency, high accuracy, very good! Ha ha ha
源代码
- 这是内部有10位ADC的一个简单应用，这个电路最多测量30 V DC，可以应用在台式电源或各种系统中的面板仪表。 PIC16F676的内部adc与一个电阻网络分压器用于测量输入电压，用数码管来显示电压值，频率在50HZ左右 在原理图中的47K看到和10K电位连接分压器配置。在默认情况PIC微控制器ADC参考电压设置到VCC（+ 5V在这种情况下），分出最大射程30伏到5伏这样的分压器。(This is a simple application with 10 bit ADC insi
AD9512_SPI_Config
- 用户可以通过各分频器改变一路时钟输出相对于其它时钟输出的相位，这种相位选择功能可用于时序粗调。(The user can change the clock all the way through the frequency divider output relative to other clock output phase, the phase selection function can be used for timing coarse adjustment.)
clock
- there's a clock divider for DE2 altra board clock (50MHz)
ds819_div_gen
- DS819数据手册 LogiCORE IP Divider Generator v4.0(LogiCORE IP Divider Generator v4.0)
guan 27
- 分频器分频为2Hz后，使计数时间变为0.5秒一个，将此时的频率传给计数器，计数器计数的变化时间就变为0.5秒一变然后再用数码管显示出数字的变化，即可得到一个从0~9变化的计时器。 文件名为随便起的项目名称，使用时如果更改需要和代码中的实体名等一起更改(Frequency divider for 2Hz, the counting time is 0.5 seconds a, the frequency to change the time counter counter becomes 0.
verilog四则运算器
- verilog四则运算，包括加法器、乘法器、除法器，不过都是拾人牙慧，整理一下，供新手参考。(Verilog four operations, including the adder, multiplier and divider, but are written, tidy, for novice reference.)
LAB #8
- 1. 請完成一個1HZ除頻器 2. 請完成一個計數器 3. 在依據需求完成計數解碼 4. 組成一個紅綠燈 (綠燈5秒, 黃燈隔秒閃爍4秒, 紅燈3秒 )(Traffic lights 1. please complete a 1HZ divider 2. please complete a counter 3. to complete counting decode according to the requirements 4. a red and green light (5
vhdl_time
- it is a clk divider
view_large_pics_41280779937
- 2014年4月14日 - 波导缝隙阵带宽总结_机械/仪表_工程科技_专业资料。波导缝隙阵带宽总结一, 改善...功分器如图2所示 图2 波导功分器示意图 应用传统方法设计计算波导尺.(April 14, 2014 - slot array _ / instrument _ bandwidth summary mechanical engineering technology _ professional information. The width of the waveguide slot a
divider fpga4student
- 46bit devider with verilog language
ise
- 在ise软件上，用VHDL语言，设计的数字跑表，可以两位计数，含分频器，计数器(In the ISE software, using VHDL language digital stopwatch design, can two counts, including frequency divider, counter)
plj
- 使用vhdl语言原件例化设计数字频率计，并用6位7段数码管计数。模块包括：十进制计数器，6位10进制计数器，Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。(The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6
全能抽奖软件下载 v7.0.2.5 绿色免费版
- 东方的说法更好地发挥更大方风格化东方红的分隔号的分隔号(The Oriental view gives better play to the more generous style of the divider of Oriental Red)