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ddr_usb
- 将256位数据宽度 通过两级FIFO 转成16位 使用XILINX的ISE10.1完成设计 此为工程文件 有仿真结果-The 256-bit data width conversion FIFO through the two 16-bit using the XILINX s ISE10.1 to complete the design documents for the works in this simulation results
fifo
- 同步FIFO设计一个同步FIFO,该FIFO深度为16,每个存储单元的宽度为8位,要求产生FIFO为空、满、半满、溢出标志。请采用可综合的代码风格进行编程。-Synchronous FIFO design a synchronous FIFO, the FIFO depth is 16, the width of each memory cell is 8, required to generate the FIFO is empty, full, half full, the overflow
SDRAM_LCM_PROJECT
- sdram源代码,输入16数据位数据到sdram,再传送到fifo,通过uart端口发送出去。-sdram source code, data input 16-bit data to sdram, then transmitted to the fifo, sent through uart port.
fifo_verilog
- 16位FIFO的硬件电路,使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现,以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code