搜索资源列表
VerilogHDL
- 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure an
Fir-40ntap-4order
- Fir filter with 40tap, 4 order
FIR
- FIR滤波器的一种新型设计方法 讲述型的快捷的方法来设计滤波器-无
coe
- 自动计算fir滤波器系数的工具，不妨一试-Automatic calculation of filter coefficients fir tools, try
fir_16
- vhdl代码 实现16阶fir滤波器，可以仿真通过-vhdl code fir filter stage 16 can be adopted simulation
FIR
- 基于FPGA的FIR滤波器实现，含全部不源代码-FPGA-based FIR filter, including all non-source code
IIR
- 毕业设计：基于FPGA的IIR滤波器设计-The design for IIR digital filter based on FPGA
fir
- 只是一个8阶的fir滤波器，希望对大家有用-Only an 8-band fir filters, useful for all of us hope
f
- vhdl code for FIR filter
filter
- FIR数字滤波器的实现，采用Kaiser窗实现高精度的地痛滤波器。-The realization of FIR digital filter using Kaiser window filter to achieve high accuracy in pain.
hdlsrc
- vhdl program to implement symmetric fir filter
Filter
- FIR滤波器~在ISE下运行成功~格形滤波器-FIR
Order17firfilter
- 17阶FIR滤波器VHDL代码及说明文档-Order 17 FIR filter based on VHDL
fir
- 是一个fir滤波器 其中使用了MAC单元去实现累加和乘法运算。-A fir filter which uses the MAC unit to achieve accumulation and multiplication.
fir48
- 48阶FIR设计，采用VHDL语言描述，门级映射-48-oders FIR design with VHDL language and gate level
filter
- 各种模块实现10阶FIR滤波器,用matlab中的fdatool计算出设计的滤波器的系数，再利用VHDL编写各模块程序，实现滤波器-Various modules to achieve the10order filter based on FIR, using MATLAB FDATool calculates the design of the filter coefficients, then use VHDL to prepare procedures for each module, t
fir
- 本历程是用 VHDL实现fir滤波器cds算法的历程，熟悉CDSsuanfa -This process is to achieve fir filter algorithm cds course, familiar with CDSsuanfa
FIR
- Filtres Fir in VHDL with integer coefficients
VHDL-FIR-filters
- ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has be
E4_6_FirIpCore
- 用vhdl语言在xilinx上用ip核实现的fir滤波器的设计(Design of FIR filter implemented with IP kernel on Xilinx in VHDL language)