搜索资源列表
I2Cdesign.rar
- I2C总线Verilog源代码描述，ModelSim仿真,I2C bus Verilog source code descr iption, ModelSim Simulation
IIC_VHDL
- I2C总线的FPGA描述，基于FPGA平台的两线制串行通信协议的硬件模拟，采用VHDL语言描述。-Inter Integrated Circuit in VHDL
I2C
- 详细描述了I2C的技术规范 版本号为2.1 是采用VHDL编写I2C的IP核的一本不错的参考资料-A detailed descr iption of the I2C specification version 2.1 is the use of VHDL for the preparation of the IP core I2C a good reference
I2C
- IIC通信协议IP核，描述IIC协议在FPGA上的实现-IIC communications protocol IP core
i2c.tar
- I2C verilog HDL code including test environment
vhdlshili
- 多个vhdl 实例，USB UART I2C VGA-vhdl USB UART I2C VGA
I2C_Verilog
- I2c控制器的verilog代码及说明文件-verilog code and notes of i2c controller
i2c_verilog.tar
- i2c的逻辑设计实现，有详细的文档说明，供大家学习使用-i2c Design and Implementation of the logic, the document explains in detail for them to learn from the use of
I2CSLAVE
- 已经验证过的I2C，slave的IP，core，从一开源网站下载的，代码写的非常好，节省了FPGA的资源，比起以往的slave的CORE，这个CORE减少了寄存器的使用。-Has been verified I2C, slave of the IP, core, from an open source website, the code is written in a very good save FPGA resources than the previous slave of CORE, t
ds32c35
- ds32c35是dalas生产的实时时钟（RTC）芯片，本程序（在EP2C8Q208C8N上调试通过）在FPGA上构建I2C接口于此时钟芯片通信。可以在LED上动态实时显示时间。利用本程序也可以改编成高精度实时时间测量的程序-ds32c35 is produced by dalas real-time clock (RTC) chip, this program (in the EP2C8Q208C8N debugging via) in the FPGA built this clock ch
i2c
- i2c master controller, free ip
I2C_SLAVE
- I2C slave端。可支持1带多。本人已经过调试，确认是可用的。-I2C slave side. Can support more than one band. I have been debugging, sure there is available.
i2c_slave
- I2C 从设备通讯程序，用于I2C 硬件设计-I2C slave communication program, used to for I2C HW design
I2Cvhdl
- 采用vhdl语言编写的串行总线I2c程序-The serial bus I2c procedures using VHDL language
IPCores_iic_8051
- I2C_IP_Core, 使用VHDL 和VERLOG编写，并有文档说明-I2C IP Core, VHDL/Verilog
TEMPERATURE_MONITOR
- I2C type Temperature monitor sensor access logic by VHDL.
I2C
- 基于FPGA的IIC IP硬核设计 连接UC系统，用VHDL语言书写
i2c_master
- This details an I2C master component for single master buses, written in VHDL for use in CPLDs and FPGAs. The component reads and writes to user logic over a parallel interface. It was designed using Quartus II, version 11.1. -This details an I2C mas