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shuzidianzizhong
- 此次设计与制做数字钟就是为了了解数字钟的原理，从而学会制作数字钟.而且通过数字钟的制作进一步的了解各种在制作中用到的中小规模集成电路的作用及实用方法.且由于数字钟包括组合逻辑电路和时叙电路.通过它可以进一步学习与掌握各种组合逻辑电路与时序电路的原理与使用方法.-Design and production of the digital clock digital clock in order to understand the principle, so learn to create digit
szmms
- 本文的电子密码锁利用数字逻辑电路，实现对门的电子控制，并且有各种附加电路保证电路能够安 工作，有极高的安全系数。 -In this paper, electronic locks using digital logic circuits, the realization of the electronic door control, and a variety of additional circuitry to ensure that the circuit can work in s
Simulator
- C实现模拟与或非门的逻辑电路，可以多元件输入，支持元件延时，可以绘制输出波形-C simulation and implementation of logic circuits or door, you can enter many components to support the delay components, you can draw the output waveform
DigitalLogic
- 组合逻辑电路、时序逻辑电路及数字逻辑电路系统的设计、安装、测试方法-Combinational logic circuits, sequential logic circuits and digital logic circuit system design, installation, testing methods
vhdl
- 实现代码，A、B为输入、Y为输出，它们为8位向量。OE为输出使能，低电平有效。IE为输入锁存时能，上升沿有效。Ci为进位输入，Co为进位输出。 S0、S1、S2为运算逻辑选择输入： ，用vhdl语言编写，基于数字电路。-Implementation code, A, B input, Y the output, they are 8-bit vector. OE to output enable, active low. IE when the input latch, rising e
DE2_NIOS_HOST_MOUSE_VGA
- 显示控制电路是整个场序彩色显示【15】【16】系统的心设计部分,本文采用Verilog HDL来设计。首先编写对各单元电路进行以行为级描述的Verilog代码,再用EDA工具对Verilog HDL代码进行功能仿真和逻辑综合。-Display control circuit is the field sequential color display 【15】 【16】 system design part of the heart, this paper Verilog HDL to desig
FPGA
- FPGA基础知识点拨，今FPGA 在复杂逻辑电路以及数字信号处理-FPGA basics of coaching, this FPGA in complex logic circuits and digital signal processing
ps2
- 数字逻辑电路实验，ps2借口的吉安帕输入输出，采用ALTER DE2—70板-Experiment, the ps2 an excuse Jian Pa input and output of digital logic circuits using ALTER DE2-70 board
TheBasicLogicFamiles-DL
- DIODE LOGIC CIRCUITS TUTORIAL
VHDL-four-selected-a-data-selector
- 数字电路与逻辑设计实验 四选一数据选择器VHDL语言实现-Digital circuits and logic design experiments four selected a data selector VHDL language
fifo_verilog
- 16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
SimpleTruthTable.tar
- 用c++写的逻辑表达式真值表，可以实现 a&!(b|c)的真值表。特点是代码简短，风格规范，注释少而精。适合离散数学和模拟电路课程的学习。 tar.gz包内有README，按里面写的编译运行。-With c++ Write truth table logic expressions, you can achieve a & (b | c)! Truth table. Is characterized by a short code, style norms, comment concise.
fifoas
- 异步时序的FIFO，实现了异步逻辑的电路，可综合，通过了验证-Asynchronous timing FIFO, implement asynchronous logic circuits can be integrated through the verification
LogicCircuits
- 用图中寻找最短路径的方法生成可逆逻辑电路-create logic circuits using the way of finding shortest path in the graph
DIY数字电桥V3.0
- 液晶电压表\ADC0809.asm 液晶电压表\0809.plg 液晶电压表\ADC0808.PWI 液晶电压表\液晶_Uv2.Bak 液晶电压表\STARTUP.A51 液晶电压表\液晶.plg 液晶电压表\STARTUP.LST 液晶电压表\ADC0809.LST 液晶电压表\液晶.lnp 液晶电压表\液晶.M51 液晶电压表\液晶.hex(Figure 3. Timing diagram 10, 16Phase This TTL-compatible
L5 - Combinational Logic Design with Verilog
- combinational circuits