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8-bit_multiplier
- 用ASM原理做二進位8-BIT乘法的乘法器,內附範例的輸入檔。-ASM to do with the principle of binary multiplication of 8-BIT multiplier, the input file containing a sample.
8bit-multiplier
- 8位二进制数乘法器VHDL实现8位二进制数乘法器设计,乘法通过逐项移位相加原理来实现,从被乘数的最低位开始,若为1,则乘数左移后与上一次的和相加;若为0,左移后以全0相加,直至被乘数的最高位。 -8-bit binary multiplier VHDL 8-bit binary multiplier design, multiplication by itemized shift sum principle, starting from the least significant bit of
VHDL-Code-for-8-bit-Floating-Point-Multiplication
- VHDL Code for 8 bit Floating Point Multiplication