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EP1C3_12_7_SPCTR
- 基于FPGA的信号采集及频谱分析,用VHDL编写,压缩包里是Quartus下的工程。AD采样用状态机实现,并存入LPM_RAM。设计了一个UART模块(也是状态机实现的),可将数据发到PC机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to
digitaloscilloscope
- This digital oscilloscope takes a MCU and FPGA as the core. We made emphases on the choice of the sampling methods and the implement of equivalent sampling as a result, our design not only has the real-time sampling mode but also can reach the highes
jj
- 本题设计一个数字存储示波器,以Xilinx公司20万门FPGA芯片为核心,辅以必要的外围电路(包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块),利用VHDL语言编程,实现了任意波形的单次触发、连续触发和存储回放功能,并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时,将外部输入信号经信号调理模块调节到A/D电路输入范围,经A/D转换后送入FPGA内部的双口RAM进行高速缓存,并将结果通过D/A转换送给通用示波器进行显示,完成了对中、低频信号的实时采样和高频信号的等效采
VGA_CHAR_WAVE
- FPGA 示波器,使用 digilent 的 nexys2 板子。可以在 VGA 显示器上显示波形及字符。AD 为 60M 采样频率 8bit 的 ADS830E 。-The FPGA Oscilloscope, use digilent, the nexys2 board. Waveform can be displayed on a VGA monitor and character. The AD for 60M sampling frequency 8bit ADS830E.
FIR5
- FPGA基于FIR的滤波,EP2C8芯片 40Mhz的采样频率,50KHz的截止频率的低通滤波,自己调试可用-FPGA-based FIR filter, EP2C8 chip 40Mhz sampling frequency, 50KHz cutoff frequency of the low pass filter, own debugging available
ADC_TLC549-TEST
- TLC549AD采样程序 在数码管上显示,我们的TLC549AD是独立的模块,没有直接和FPGA链接,所以我们在使用时,要用杜邦线链接起来。-TLC549AD sampling program on the digital display, we TLC549AD are independent modules, and FPGA no direct link, so we use, use DuPont wire linked.
SPWM信号产生系统IP软核设计及验证
- 针对电力电子领域的需求,采用自然采样法设计了一个全数字三相SPWM信号产生系统IP软核.通过数字频率合成技术实现了对电源频率的辅确控制.使电源频率精度达到16位.其中。通过调节控制参数.分别实现了电源频率与载波频率的7级、8级控制.最后。搭建了基于FPGA的测试系统.验证了系统功能的正确性.(According to the requirement of power electronics, the natural sampling method for the design of a full
中频采样QPSK解调的FPGA设计与实现_杨波
- 中频采样QPSK解调的FPGA设计与实现_杨波(Yang Bo _ FPGA design and implementation of intermediate frequency sampling QPSK demodulation)