搜索资源列表
FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
63535309sram
- verilog编写的读写SRAM的源码，包括sram的读写控制-SRAM read and write verilog source code written in, including the sram to read and write control
verilog_SRAM-test
- verilog 进阶实验_SRAM：SRAM 测试-verilog Advanced experimental _SRAM: SRAM test
sync_fifo
- Verilog HDL code for synchronous SRAM FIFO
gds8k_32bit_1M
- 一款SRAM的verilog代码及版图信息-verilog codes and layout information of a RAM
bus_ahb_to_sram
- amba ahb to sram verilog
S21_SRAM
- 红色飓风fpga开发板提供sram驱动程序，verilog实现，想学习FPGA同学一定要参考并使用，挺实用-FPGA verilog sram
ad_prj1.4.3
- AD采集固定点数FPGA对采集数据进行指定次数累加，存储至片外SRAM并等待上位机发送取数据指令(The AD acquisition fixed point number FPGA adds the number of data to the collected data, stores it to the outside SRAM and waits for the upper computer to send the data instruction)
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)