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binary_to_bcd
- this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres
traffic
- verilog交通灯程式，分别A方向和B方向的交通灯,-verilog of traffic light system,which are A direction and B direction of traffic light.
verilog
- 设计可以对两个运动员赛跑计时的秒表:(1）只有时钟（clk）和一个按键（key），每按一次，key是持续一个时钟周期的高电平脉冲 （2）秒表输出用0－59的整数表示 （3）key： （A）按一下key，开始计数； （B）第一个运动员到终点时第二下key，记住时间，继续计数； （C）二个运动员到时按第三下key，停止计数； （D）然后按第四下key，秒表输出第一个运动员到终点的时间，即按第二下key时记住的计数值； （E）按第五下key，秒表清0。 -Design
FuShu_SignedAmultB_AB
- FPGA Verilog计算 A*conj(B) 有符号定点数：复数相乘模块 共轭模式 -FPGA Verilog computing A* conj (B) signed fixed point: complex multiplication module conjugate mode
PLDexp1
- PLD实验B组实验一，旋转开关，使用verilog代码-PLD experimental group B experiment a rotary switch, use the verilog code
4052125multiplier
- he multiplication operator in Verilog is leads to what is called a context-determined expression. The width used for the arithmetic in a self-determined expression depends on the widths of the operands and the result. With assign c = a*b;. th