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UEworldfile
- 能够在Ultraedit中高亮显示verilo、verilog2001、vhdl、vhdl93、fortran90、fortran95、PythonSYS、php5、oraclesql、MySQL5、flash5等多达400多种编程语言的语法。-can highlight grammar of more than 400 programming languages such as verilo,verilog2001,vhdl,vhdl93,fortran90,fortran95,PythonS
hem.dds
- dds编程代码 希望对别人有帮助 其功能是根据dds的原理编写，实现其功能模块-dds vhdl
D_clock
- d_clck的VHDL语言编程，实现d_clke的功能 -d_clck
beep
- 通过改变频率使蜂鸣器发出不通声音。VHDL语言 编程FPGA-By changing the frequency so that the issue of access to the voice of buzzer
pll
- 摘要:叙述了全数字锁相环的工作原理,提出了应用VHDL 技术设计全数字锁相环的方法,并用复杂可编程逻辑器件CPLD 予以实现,给出了系统主要模块的设计过程和仿真结果。-Abstract: This paper describes the working principle of an all-digital phase-locked loop is proposed application VHDL technical design an all-digital phase-locked loo
lab_text
- EDA考试的五种题目编程，其中包括五人表决器，抢答器，乘法器，自动售货机等， 编译环境为ISE，程序语言VHDL-eda text ise vhdl
jj
- 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采
sift-0[1].9.18.tar
- 用sift算法进行图像的匹配。可以两幅不同的图像中进行点对点的匹配。很好的图像匹配的算法。用matlab编程-Using sift algorithm for image matching. Two different images can be carried out point to point matching. A very good image matching algorithms. Programming using matlab
VHDL
- VHDL硬件语言教程,用于FPGA等的硬件编程语言-VHDL language using in FPGA
100503
- FPGA有价值的27个编程例子。包括LED控制，LCD控制，ASK调制与解调，DAC0832接口电路程序-27 example about FPGA
qiangdaqi
- 抢答器，用vhdl语言编程，在fpga平台上实现。-Responder, with the vhdl language programming, in fpga platform to achieve.
CPLD
- 关于对CPLD的VHDL编程，通过几个例子可达到对软件熟悉的目的，对于进一步学习很有帮助，建议初学者看一下-VHDL on the CPLD' s programming can be achieved through several examples are familiar with the purpose of the software, very helpful for further study is recommended for beginners to look at
dds_quicklogic
- 关于信号发生器的VHDL编程，很好的程序，可供大家参考学习，-VHDL programming on the signal generator, a good program, for your reference study, huh, huh
DDS
- 基于FPGA的DDS的相位累加器详细介绍,是VHDL编程,利用quartus2平台.-Design of Direct digital synthesis Signal Generator
test
- 简易计算器 2位数字的加减乘除 用VHDL编程 在实验箱上实现-Simple Calculator 2-digit addition and subtraction, multiplication and division using VHDL programming to achieve in the experimental box
539407280_1_homework1
- VHDL练习题，认真练习VHDL练习题有利于提高VHDL编程能力成为一硬件编程高手。-VHDL exercises seriously practice VHDL exercises will help improve the VHDL programming capabilities into a hardware programming expert.
diancilu-vhdl
- 使用软件quartus 进行VHDL编程实现电磁炉的烹饪模式选择，档位控制，以及加热时间，及自动计时完成时结束加热，并通过数字逻辑电路实验板进行模拟。-Quartus conducted using VHDL programming software cooker cooking mode selection, when the end of the heating gear control, as well as the heating time, and automatic timing i
1khz-square-wave
- 基于quartus ii的vhdl编程 产生1k方波-1k produce a square wave quartus ii vhdl based programming
mydds
- 通过VHDL编程，在FPGA内实现DDS模块生成正弦波-Through VHDL programming, within the FPGA to realize DDS module to generate sine wave
outTraeskitter
- VHDL编程 out std_logic Transmitter control DataBits in st-VHDL programming out std_logic- Transmitter control DataBits in st