该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the output repo

基于ARM处理器的基4和基5的FFT算法标准C程序，作者是JDB。-Base on ARM processor about Radix 4/5 FFT routines supporting 16/64/256 and 20/80 calculations. The source originally contributed by JDB