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3des_vhdl
- DES-3 VHDL Code implemented on FPGA ,including related document
tripledes
- 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
des3
- The best 3des code. The best area
aes_thesis_v1.0
- AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
DES_Encrypt_Decrypt_Verilog
- DES加密算法的Verilog HDL实现，带模式选择端口，可以实现加密和解密，已经modelsim仿真通过。-Des En/Decrypt,Verilog HDL code
topic
- DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA