搜索资源列表
MD5(verilog)
- MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
SHA1的VERILOG 实现，内含测试代码
- SHA1的VERILOG 实现，内含测试代码，经过了验证 -SHA1 implementation of VERILOG, containing test code, and proven
基于verilog的38译码器
- 基于verilog的38译码器，八个输出，三个输入-counter based on verilog
DES.rar
- DES算法的verilog实现，实现了硬件IC对DES的构架，可以直接应用在系统当中。,DES algorithm Verilog realized, the realization of the hardware IC framework of DES, can be directly used in the system.
CRC.rar
- Verilog写的 CRC 编码 ,CRC code written in Verilog
aes-verilog-imp
- AES加密算法的硬件实现，硬件语言为verilog-AES encryption algorithm hardware implementation, hardware verilog language
rom_des
- DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
lfsr
- 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
md5_latest[1][1].tar
- MD5算法verilog代码，很不错的，可以互相交流学习-MD5 algorithm verilog code, and a very good
DES_Verilog
- 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test
armok01120613
- arm verilog的相关代码 仅仅供学习使用-arm verilog code only for the relevance of learning to use
sha_core
- 安全散列函数的VERILOG实现，通过了fpga验证，在系统正可以直接当IP盒应用-Secure Hash Function VERILOG achieve, through the FPGA verification, the system is can be directly applied when the IP box
sha1_verilog
- 安全散列算法的另一种verilog实现，对面积的要求更小，但损失了速度，但在一般系统中，完全可以满足大部分需要了-Secure Hash Algorithm another Verilog realization of the demands of a smaller area, but a loss of speed, but in the general system, fully satisfy the needs of the most
8086IP
- 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
sha256_512
- Verilog实现的SHA256/SHA512算法，已仿真和验证-Verilog implementation of SHA256/SHA512 algorithm, simulation and verification has been done.
fpadd
- 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
GF_MUL
- Galois域乘法器的Verilog源码 广泛用于信道编码、计算机代数及椭圆曲线加密等-Galois field multipliers are widely used in the Verilog source channel coding, computer algebra and elliptic curve encryption
sha
- 内带3个sha1的C源码。经验证都可用。在我们项目中，已经用于验证SHA1的verilog-With three within the C source code sha1. Experience certificate are available. In our project, has been used to validate SHA1 of verilog
aes_core
- aes_core verified verilog ip core-aes_core verified verilog ip core
ECDSA_Verilog
- 椭圆曲线加解密算法的verilog实现，帮助初学者有效理解ECC算法。-Elliptic curve encryption and decryption algorithm verilog implementation, to help beginners understand the ECC algorithm is effective.