搜索资源列表
rijndaelimplemetation
- rijndael算法的一个vhdl语言编写的程序,可供学习者参考交流-a VHDL language procedures, exchange of information for learners
aes-vhdl 使用vhdl语言实现aes（rijndael 算法）
- 使用vhdl语言实现aes（rijndael 算法），程序整体封装成为一个package，方便调用-Using vhdl language aes (rijndael algorithm), the program as a whole package as a package, easy call
vh2sc
- 将VHDL转换为C的软件 将VHDL转换为C的软件-VH2SC is a free basic VHDL to SystemC converter. The converter handles a small subset of Synthesisable VHDL 87/93 language constructs. The current version translates all VHDL IEEE types to sc_int/sc_uint/integers and boole
hundunjiami
- 混沌加密应用于实际电路的VHDL语言编写的电路选通程序。-Chaotic encryption used in the actual circuit of the circuit VHDL language gating process.
freehdl-0.0.6.tar
- inplementation of AES vhdl The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm
jijiaqi
- 利用ＶＨＤＬ语言实现的实用出租车计价器程序 -The practical use of VHDL language implementation procedures Taximeter
tongxunjiekou
- 基于VHDL语言，实现串行通讯接口功能的主程序-The use of VHDL language implementation of the serial communication interface program
Watchdog
- 基于ＶＨＤＬ语言，实用的看门狗功能设计程序-Based on the VHDL language, and practical watchdog function of the design process
Multiplier
- 基于VHDL语言，实现串并乘法器设计主程序-Based on the VHDL language, to achieve the main program string and Multiplier Design
gaocengdianti
- 基于VHDL语言，实现高层电梯控制器设计程序-Based on the VHDL language, to achieve high-rise elevator controller design process
AES_verilog
- AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
DES
- VHDL语言编写的DES算法，可以参考一下。 -VHDL language of the DES algorithm for reference.
AES
- 详细描述了AES加密算法的过程及S盒变换，用VHDL语言描述，通俗易懂-AES encryption algorithm is described in detail the process and transform S box, with the VHDL language to describe, easy to understand
ADC0809
- 应用VHDL语言实现了模数转换，利用的是adc0809-Application VHDL language realized the modulus conversion，Taking advantage of the adc0809
weisuiji
- 伪随机码系统器件发生器 产生伪随机序列 使用VHDL 语言开发设计，编写长度不长，只有20多行-Pseudo-random code system device generator produces pseudo-random sequence using VHDL language development and design, write the length is long, only 20 more lines
ECCP
- ECC Cryptography using Hardware definition language especially VHDL.
DES-S
- des加密算法在MATLAB中，通过VHDL语言的实现-des encryption algorithm in MATLAB, through the realization of VHDL language
aes_thesis_v1.0
- aes code in verilog vhdl language which is very useful.