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cla_src
- carry lookahead adder verilog program
fpadd
- 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
d10-counter
- 十位加法器，用verilog语言编写，适用于verilog学习。-10-bit adder, using Verilog language, applicable in verilog learning.