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DP_RAM_lab
- 用SmartGen 生成一个2k*8 Dual Port RAM,并通过串口发送数据初始化RAM。然后通过串口返回到上位机的串口调试程序显示。-SmartGen generated using a 2k* 8 Dual Port RAM, and sending data through the serial port to initialize RAM. And back through the serial port to the PC serial port debugger displ
seven_seg
- 环境VHDL,工具quartusII,结合EDA实现,实现功能七段扫描显示-Environmental VHDL, tools quartusII, combined with EDA, achieving functional segment scan display