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aes加密算法实现，经过FPGA验证的
- aes加密算法实现，经过FPGA验证的！,aes encryption algorithm, after FPGA validation!
sha1_v01.zip
- SHA-1加密算法的IP核，内涵文档，仿真测试文件,SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file
mulf2m.rar
- 椭圆曲线加密算法中的乘法器的生成，主要功能是实现在素域上的多项式模P(大素数）乘的运算。,Elliptic curve encryption algorithm to generate the multiplier, the main function is to achieve in the Su-domain polynomial module P (large prime numbers) by the operator.
des3.rar
- 3des加密算法实现，经过FPGA验证的！,3des encryption algorithm, after FPGA validation!
DES_Verilog
- 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test
高级加密算法
- AES加密和解密源码！-AES encryption and decryption source!
IDEA_EN_TOP
- IDEA加密运算模块，运算速率100Mbps，请大家参考-IDEA encryption algorithms module, computing speed 100Mbps, please refer to
RIJNDAEL_EN_TOP
- AES加密运算模块，运算速率100Mbps，请大家参考-AES encryption algorithms module, computing speed 100Mbps, please refer to
SHA1_TOP
- sha_1加密运算模块，运算速率100Mbps，规格512位请大家参考-encryption algorithms sha_1 module, computing rate of 100Mbps, the specifications please refer to 512
sha
- sha加密算法实现，经过FPGA验证的！-sha encryption algorithm, after FPGA validation!
GF_MUL
- Galois域乘法器的Verilog源码 广泛用于信道编码、计算机代数及椭圆曲线加密等-Galois field multipliers are widely used in the Verilog source channel coding, computer algebra and elliptic curve encryption
rc5statemac
- rc5 encryption- rc5 encryption using vhdl, using state machine, more detailed descr iption can be found in ieee papers.
t3_enc
- triple des encryption decryption
tripledes
- 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
rsa
- 用VHDL求rsa加密系统的密钥D（辗转相除法）-Using VHDL for rsa key encryption system D（Division algorithm）
AESsim
- AES alogrithm security encryption
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
AES_verilog
- AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
AES_128
- 128 bit Advanced Encryption Standard
DES-Encryption
- VHDL Encryption/ Decryption Algorithm