基于Fermat数变换的大数相乘运算的Verilog实现，可应用于RSA加法芯片中。-Fermat number transform based on multiplying large numbers operations Verilog implementation, can be applied to RSA chip.

基于脉动结构的有限域乘法器，verilog代码-Based on the pulse of the structure of finite field multipliers, verilog code

该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns

基于Quartus ii 平台的DES加密算法Verilog设计和modelsim仿真(DES encryption algorithm design and Modelsim simulation based on Quartus II platform)