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DES_16keys用VC生成DES加解密算法的16轮密钥
- 用VC生成DES加解密算法的16轮密钥， 可直接用于编写DES的VHDL的密钥生成模块 -Generated using DES encryption and decryption algorithm VC 16-round keys can be directly used to write the VHDL DES key generation module
HMAC-MD5
- HMAC — MD 5算法的硬件实现，可以对初学者有一定得帮助。-HMAC- MD 5 algorithm for hardware implementation
DES_Verilog
- 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test
高级加密算法
- AES加密和解密源码！-AES encryption and decryption source!
IDEA_DE_TOP
- IDEA解密运算模块，运算速率100Mbps，请大家参考-IDEA decryption computing module, computing speed 100Mbps, please refer to
RIJNDAEL_DE_TOP
- AES解密运算模块，运算速率100Mbps，请大家参考-AES decryption computing module, computing speed 100Mbps, please refer to
rc5decstmac
- RC5 decryption algorithm implementation, using vhdl, with state machine implementation, use ieee papers for more detailed descr iption.
t3_enc
- triple des encryption decryption
AES_verilog
- AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
DESsuanfa
- DES的加解密算法的实现，无错，非常适合毕业设计运用-DES encryption and decryption algorithm, error-free
avs_aes_latest.tar
- AES algorithm decryption Encryption
AESvhdl
- AES vhdl, encryption, decryption code
Advanced-Encryption-Standard-(AES)
- AES decryption standards, vhdl code
aes_imp
- AES CODE IN VHDL FOR ENCRYPTION AND DECRYPTION
AES-Encryption-VHDL-master
- AES Encryprtion an decryption algorithm
IDEA-decryption-HDL-code
- Decryption code for IDEA algorithm in VHDL