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这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test
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Verilog实现的SHA256/SHA512算法，已仿真和验证-Verilog implementation of SHA256/SHA512 algorithm, simulation and verification has been done.
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该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the output repo
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这是一段verilog的调用测试例子，可以以此作为参考，对其他verilog仿真时，进行调用。-This is a verilog call the test example, can be used as a reference, on the other Verilog simulation call.
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AES128的verilog实现，仿真通过。-AES128 the verilog achieve, through simulation.
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用于国密4的加解密算法实现，采用verilog 语言，可进行vivado仿真，vivado版本是2013，结果经测试正常，适合从事相关行业的工作人员进行借鉴和开发。(The code is realized and simulated by verilog. The simulation result has been confirmed by the author. It is recommended to download by the researchers who are in the
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基于Quartus ii 平台的DES加密算法Verilog设计和modelsim仿真(DES encryption algorithm design and Modelsim simulation based on Quartus II platform)
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