搜索资源列表
hmac-zy
- hmac的verilog代码, 通过控制字选择进行sha1运算或hmac运算-hmac the verilog code word through the control options or hmac sha1 Operational Operational
CODE
- DES encryption for verilog program
SHA1的VERILOG 实现，内含测试代码
- SHA1的VERILOG 实现，内含测试代码，经过了验证 -SHA1 implementation of VERILOG, containing test code, and proven
CRC.rar
- Verilog写的 CRC 编码 ,CRC code written in Verilog
lfsr
- 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
class
- RC5/RC6 Base加密/解密源码 -RC5/RC6 Base encryption/decipher source code
crc1
- CRC编码verilog代码，用于实现crc编码功能-CRC coding Verilog code for CRC encoding capabilities to achieve
crc
- 这是CRC字符串校验的源码，可对字符串校验后输出校验码-This is the CRC checksum of the source string can be output after the string checksum validation code
crc
- CRC校验码的实现，校验码6位，寄存器串行实现方式，经项目实际验证正确-CRC Check Code realization Check 6, register serial ways, the right to verify the actual project
sha
- 内带3个sha1的C源码。经验证都可用。在我们项目中，已经用于验证SHA1的verilog-With three within the C source code sha1. Experience certificate are available. In our project, has been used to validate SHA1 of verilog
tripledes
- 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
md5.tar
- MD5 Hash Verilog code
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
aes_crypto_core_latest.tar
- verilog code for aes
aes_thesis_v1.0
- AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
rtl
- 基于脉动结构的有限域乘法器，verilog代码-Based on the pulse of the structure of finite field multipliers, verilog code
DES_Encrypt_Decrypt_Verilog
- DES加密算法的Verilog HDL实现，带模式选择端口，可以实现加密和解密，已经modelsim仿真通过。-Des En/Decrypt,Verilog HDL code
topic
- DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA
64R4SDFpoint_FFT
- 该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the output repo
ecc_verilog code
- ELLIPTIC CURVE CRYPTOGRAPHY VERILOG CODE