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liuVHDL.rar
- 一种基于状态机设计的串并行转换电路，将LTC1196(ADC)的串行输出数据转换成并行数据的转换电路， ADC的时钟由转换电路提供，,Design a state machine based on parallel conversion circuit of the series will be LTC1196 (ADC) output of the serial data into parallel data conversion circuit, ADC clock provided by
8b10b_pdf
- 8b10b编解码设计的pdf文章,用于现代千兆网通信,快速串行通信.-.pdf paper
liuVHDL
- 一种基于状态机设计的串并行转换电路，将LTC1196(ADC)的串行输出数据转换成并行数据的转换电路， ADC的时钟由转换电路提供，-Design a state machine based on parallel conversion circuit of the series will be LTC1196 (ADC) output of the serial data into parallel data conversion circuit, ADC clock provided by
rei2c
- 用VHDL编写的quartusii平台上的串行EEPROM配置读取的程序。-Quartusii prepared using VHDL platform to read the serial EEPROM configuration procedures.
serialcomvhdl
- 一个串行通信的例子，用vhdl实现。包括发送接收，分频等多个模块-Example of a serial communication with the realization of vhdl. Including the transmission of the reception, a number of modules, such as Frequency Division
vhdl
- VHDL语言的UART串行接口芯片设计程序清单 附录1 数据接收据器的VHDL语言描述清单-vhdl serial
i2cBUS
- I2C总线是一种非常常用的串行总线，它操作简便，占用接口少。本程序(verilog hdl)介绍操作一个I2C总线接口的EEPROM AT24C02 的方法，使用户了解I2C总线协议和读写方法。-The I2C bus is a very common serial bus, it is simple, occupy less interface. This program (verilog HDL) introduced operating a AT24C02 EEPROM of I2C
Interface
- 已在实验箱上验证,目标芯片EP1C3T144C8 十位全时双工串行通信接口-Interface
UART_rec
- 422收到数据，串行转并行，VHDL编程，12M的时钟-DATA TRANCEICE
用FPGA实现UART
- 用fpga实现异步串行通信。通过串口助手接收与发送(Implementation of serial communication with FPGA)
counter_displayer
- 基于fpga的vhdl数码管显示模块。已经译码，采用串行数据。(number displar base on vhdl)