搜索资源列表
uart.rar
- 实现串并口通信,共有发送和接受两个模块。,Strings parallel to achieve communication, send and receive a total of two modules.
ofdm-vhdl.rar
- ofdm的VHDL实现，包括fft,ifft,串并变换等，附详细说明文档,ofdm realization of VHDL, including the fft, ifft, such as string and transform, with detailed descr iption of the document
CPLD_USB
- ：CPLD 可编程技术具有功能集成度高、设计灵活、开发周期短、成本低等特 点。介绍基于ATMEL 公司的CPLD 芯片ATF1508AS 设计的串并转换和高速 USB 及其在高速高精度数据采集系统中的应用-: CPLD programmable technology with a high degree of functional integration, design flexibility, short development cycle, and low cost. ATMEL-b
cjq_firmware_combine
- 这是一个通过cpld扩张两个串口和两个并口的VHDL程序，非常适用于初学者扩张串口和并口用。-This is an expansion by cpld two serial and two parallel port of the VHDL program is ideal for beginners to use serial and parallel port expansion.
UART_VHDLCodes
- 基于VHDL的异步串口收发器，在FPGA上设计Uart接收模块实现从pc接收串口数据； 在FPGA上设计Uart发送模块，把从pc接收的数据的16进制值加1再发送给PC； 设计单片机和FPGA接口模块，把接收到的数据送给单片机，并显示在LCD上 -VHDL-based asynchronous serial transceivers Uart receive module in the FPGA design from pc to receive serial data desig
SPI_verlog
- VHDL 语言实现的串转并 SPI 等等 实现-The SPI bus is a 3 wire bus that in effect links a serial shift-- register between the master and the slave . Typically both the-- master and slave have an 8 bit shift register so the combined-- register is 16 bits. Whe
UART_CESHI
- 基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中-Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project