搜索资源列表
fifowrite
- ASIC 设计中 包存储功能的fifo，TCP/IP，以太网2的应用
mit-ofdm-wifi
- MIT关于OFDM收发器、WIFI收发器的ASIC和 FPGA硬件开发源码及资料，比较不错的资料OFDM: OFDM transceiver (transmitter and receiver), highly parameterized to cover 802.11a (WiFi), 802.16 (WiMax) and others in the future. Support for 802.15 (WUSB) is currently being worked on. 802
USB2.0
- UTMI全称为 USB2.0 Transceiver Macrocell Interface，此协议是针对USB2.0的信号特点进行定义的，分为8位或16位数据接口。目的是为了减少开发商的工作量，缩短产品的设计周期，降低风险。此接口模块主要是处理物理底层的USB协议及信号，可与SIE整合设计成一专用ASIC芯片，也可独立作为PHY的收发器芯片，下以8位接口为例介绍PHY的工作原理及设计特点。 -UTMI called USB2.0 Transceiver Macrocell Interfac
usb20_ipcore_usb_funct
- usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL descr iption suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
ebook_USB2.0_intel_tranceiver
- High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor
AX88172A_ASIX_935773
- AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller-The AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet controller is a high performance and highly integrated ASIC which enables low cost, small form factor
asic
- 帧同步 系统是保证收、发双方同步工作的重要单元。从基群的帧结构中可知，同步时隙 TSo是奇、偶帧两种形式的图案交替，即偶帧TS0时隙的D2～D8为帧同步码“0011011”， 奇帧TSo时隙的D2固定为“1”。为了提供防止伪帧定位的附加保护措施和提高比特误码 监测能力，TSo时隙中的第—位码作为循环冗余校验(CRC)码。-帧同步帧同步系统是保证收、发双方同步工作的重要单元。从基群的帧结构中可知，同步时隙 TSo是奇、偶帧两种形式的图案交替，即偶帧TS0时隙的D2～D8为帧同步码“
programmerFAQ
- PCI转USB接口的专用芯片，可同时扩展5个USB接口-PCI USB interface switch ASIC, which can extend five USB Interface
DVP_1412_DataSheet
- MPEG 4 ASIC chip with composit input and USB output
ZigBeexieyishuoming
- IEEE802.15.4无线个域网MAC层协议栈实现，用于无线个域网 ASIC 开发中-A protocol stack that supports coordinator/router/RFD nodes, tree routing, direct messaging, and indirect messaging using static binding
FPGA_ASIC-DSP和FPGA共用FLASH进行配置的方法
- 通过ASIC、DSP、CPU对FPGA进行配置(Through the ASIC, DSP and CPU on the FPGA configuration)
SystemVerilog for Design(Second Edition)
- 本文档用于使用systemverilog系统硬件描述语言做ASIC设计，深入浅出，易懂(The doc is using systemverilog system harward descr iption language to do ASIC design.The doc is easy to read,for new bird in this fact.)