任意分频器,可以实现FPGA的CLK分频功能，已通过编译-Arbitrary frequency divider can be achieved FPGA-CLK sub-band capabilities, has passed the compilation

微机实验 1、编写程序：使用8253的计数器0和计数器1实现对输入时钟频率的两级分频，得到一个周期为1秒的方波，用此方波控制蜂鸣器，发出报警信号，也可以将输入脚接到逻辑笔上来检验程序是否正确。 2、使用8253，编写一个时钟程序。 -Microcomputer Experiment 1, the preparation process: 8253 counter 0 and counter two of the input clock frequency divider, a per

数字分频器，包括分频器单位冲击响应及幅频响应-Digital frequency divider, including frequency divider unit impulse response and amplitude frequency response

实现对时钟信号的二分频和十分频，二者作为系统的两个输出(Realization of two frequency division and ten frequency division of clock signal,and the two are used as the two output of the system.)