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src
- DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output. -DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output.
divde_clk10m
- 一种带负反馈,无见相思曲的高精度锁相环,采用双D触发器实现-PLL
d_flipflop
- this is a general d-flip flop design in vhdl.
SHIXUN
- D触发器，运用VHDL语言编写，属于课程设计环节。-D flip-flop, using VHDL language, belonging to curriculum design aspects.
pseudo-sequence-vhdl
- 常用的几种伪随机序列的仿真及性能分析，进而运用组合序列的思想，尝试不同的序列以不同组合方式生成的新的伪随机序列，并用FPGA分析其性能，得出组合序列的一般的规律，借此推导出了一种新的组合序列——异族Gold组合序列。-Through simulation and performance analysis of several commonly use¬ d pseudo-random sequence in the FPGA environment, use the ideas of c
rs-code
- VHDL Code for D-Flip Flop & Matching Unit