搜索资源列表
CalculateSum
- Windows Mobile经典手机软件开发源码,加法器源码-Windows Mobile handset software development classic source, adder source
Csadder
- this carry saved adder-this is carry saved adder
adder
- 这是一个用VHDL语言描述的8位带符号加法器,希望对大家有用-This is a descr iption using VHDL, 8-bit adder with a symbol, we want to be useful
A3P030
- FPGA A3P030 CODEAdder.rar Bell.rar Comparator.rar Counter.rar FlashROM.rarUART.rar-FPGA A3P030 CODE Adder.rar Bell.rar Comparator.rar Counter.rar FlashROM.rarUART.rar
carry_select
- 上传的代码是基于Xilinx下的ISE开发平台，用Verilog语言编写的carry_select加法器。-Upload the code is based on the Xilinx ISE development platform, the the Verilog language of carry_select adder.
Addition-logic-unit
- 这是用Android编写的一个入门小程序，加法运算器。-This is an introductory applet written using Android, an adder.
add.tb
- 加法器tb文件，用与对加法器进行仿真处理，通过modusim运行，适合新手参考。(add tb file and with the adder simulation processing, through the modusim run, suitable for novice reference.)
adder
- 用hspice写了一个做了16bit kogge stone四层点操作的树形加法器静态逻辑网表，所有管子的尺寸按照0.25u的尺寸设计挂上测试文件跑以后逻辑没问题，但是按照拉贝尔那本书上讲的关于逻辑努力优化的方法优化，在输入级加了两级buffer，只对最长路径支路尺寸优化(Use HSPICE to write a 16bit kogge made stone four layer tree adder static logic netlist, all pipe sizes according
adder_test
- 使用modelsim软件编写半加法器和4位加法器，(Using Modelsim software to write a half adder and a 4 bit adder,)