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Bidirectional-Bus
- 双向总线的VHDL源代码，已经通过编译，可以在此基础上改为单向总线。
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
pci-verilog
- USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
i2c
- 用VHDL和Verilog语言编写的总线的源程序，从开源网站上下载下的，希望对大家有用-Using VHDL and Verilog source code written in the bus, from the open-source Web site to download the next, and hope for all of us
120
- 主要是1553B总线设计方面的UP和设计-Mainly 1553B bus design and design of UP
i2cBUS
- I2C总线是一种非常常用的串行总线，它操作简便，占用接口少。本程序(verilog hdl)介绍操作一个I2C总线接口的EEPROM AT24C02 的方法，使用户了解I2C总线协议和读写方法。-The I2C bus is a very common serial bus, it is simple, occupy less interface. This program (verilog HDL) introduced operating a AT24C02 EEPROM of I2C
SPI_verlog
- VHDL 语言实现的串转并 SPI 等等 实现-The SPI bus is a 3 wire bus that in effect links a serial shift-- register between the master and the slave . Typically both the-- master and slave have an 8 bit shift register so the combined-- register is 16 bits. Whe