搜索资源列表
FPGA-OFDM-VHDL
- something useful for communication,source code based on FPGA-something useful for communication. source code based on FPGA
decode.rar
- LDPC的Verilog程序源代码，包括仿真数据等。文件很大，请慢慢下载,LDPC of Verilog source code, including the simulation data. Large file, please download slowly
CIC.rar
- CIC梳状滤波器verilog源码，包括积分器，下抽级以及梳状滤波器三个部分。,CIC comb filter verilog source code, including the integrator, under the pump, as well as comb filter class is in three parts.
spi
- SPI master的verilog代码-Verilog code for SPI master
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
usbFPGAconnect
- 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, incl
ca_code_gen
- CA_Code_Generator.vhd用于生成GPS的32颗卫星的CA码程序，经过测试验证并消除了毛刺；CA_TEST_BENCH.vhd内带测试程序，直接可调用MODELSIM进行测试验证，留有用户接口，方便用户产生其他卫星的CA码。-CA_Code_Generator.vhd used to generate the 32 GPS satellites CA code program, tested and verified to eliminate the burr CA_TEST_
usb20
- 通用接口usb2.0的verilog开发代码-Common interface usb2.0 development of the verilog code
Frame_Detection
- 802.11a帧检测源码，包括帧同步，书上光盘带的源码。-802.11a frame detection source, including frame synchronization, books, CD-ROM with source code.
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
bpsk2
- 介绍qpsk解调的代码！初学者可以参考参考！比较简单.-Introduction QPSK demodulation code! Beginners can refer to reference! Relatively simple.
pro104_uart
- uart的代码，经实际运行可以通信，是xilinx uart 代码的改进，网上的xilinx uart代码有很多bug，用此代码可以改进运行。-UART code, the actual operation can be communication, xilinx uart code are improved, xilinx uart code online has a lot of bug, the code can be improved with this operation.
GPS_CA_Generator_vhdl
- GPS对应的CA短码发生电路的VHDL描述程序，附带modelsim仿真用源文件-GPS code corresponding to happen CA short circuit VHDL descr iption of the procedure, with ModelSim simulation using the source file
c_a
- GPS中C/A码产生简单的Verilog逻辑产生-GPS in the C/A code generated simple logic generated Verilog
ldpc
- 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
code_gen2
- GPS中C/A码生成电路，用于ＧＰＳ接收机中的跟踪和捕获。-GPS in the C/A code generating circuit for the GPS receiver to track and capture.
pll
- 实现同步时采用锁相环，锁相环实现的原理，及源代码，-Implementation of the principle of phase-locked loop, and the source code,
encode_finish
- Turbo码编码器的encode最上层模块，它的主要作用是连接Turbo码编码器的其他模块-Turbo code encoder encode top-level module, its main role is to connect the Turbo Code encoder other modules
cordic1.0
- this coric code is very compact.
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code