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uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
D_BLAST44
- MIMO 4*4系统D-BLAST编译码方案，利用ISE仿真环境，verilog编程实现。-MIMO 4* 4 system codec D-BLAST program, using ISE simulation environment, verilog programming implementation.
UART
- Verilog实现的UART程序，用ISE打开工程文件即可-Verilog implementation UART program, open the project file with the ISE can be
verilog_UART_100MHZ
- 自己写的verilog UART程序，前仿真后仿真，下到板子里都对，ISE的-Verilog UART write your own program, before simulation after simulation, are right next to the plate yard, ISE' s
carry_select
- 上传的代码是基于Xilinx下的ISE开发平台，用Verilog语言编写的carry_select加法器。-Upload the code is based on the Xilinx ISE development platform, the the Verilog language of carry_select adder.
yima
- Verilog语言描述38译码器功能，适用于ISE或者quartus软件-Verilog language descr iption 38 decoder function for ISE or quartus software
my_1602(can-use)
- 基于ise的1602测试程序，verilog，亲测可用-Ise of 1602 based test procedures, verilog, pro-test available
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
RISC_CPU完整代码
- 硬件实现一个完整的CPU，利用verilog编写，可在ISE上直接使用(Hardware implements a full CPU)