码数控振荡器相位累加器的位数N为32,利用verilog HDL语言在Quartus II 9.1中具体实现了载波和码NCO的设计。,The code numerically controlled oscillator phase accumulator bits N 32 verilog HDL language in the concrete realization of the design of the carrier and code NCO Quartus II 9.1.

无流水线加法器与寄存器结合在一起的相位累加器设计程序-vhdl implementation of phase accumulator without pipelines

基于流水线加法器与寄存器结合在一起的相位累加器设计程序-vhdl implementation of phase accumulator with pipeline and registers.

基于流水线的超前进位相位累加器设计程序,速度明显优于无流水线超前进位累加器-vhdl implementation of phase accumulator with pipeline and advanced carry.