搜索资源列表
USB
- 这个工程是基于FPGA与Philips的D12 USbB 1.1的完整设计，包括VHDL驱动和主机应用程序及驱动
usb
- 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码
USB2.0
- UTMI全称为 USB2.0 Transceiver Macrocell Interface，此协议是针对USB2.0的信号特点进行定义的，分为8位或16位数据接口。目的是为了减少开发商的工作量，缩短产品的设计周期，降低风险。此接口模块主要是处理物理底层的USB协议及信号，可与SIE整合设计成一专用ASIC芯片，也可独立作为PHY的收发器芯片，下以8位接口为例介绍PHY的工作原理及设计特点。 -UTMI called USB2.0 Transceiver Macrocell Interfac
dataacquisitionwithFPGA
- 用fpga+usb显现的4通道800K的数据采集方案。-Fpga+ usb with emerging 4-channel data acquisition program of 800K.
usbFPGAconnect
- 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, incl
usb20_ipcore_usb_funct
- usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL descr iption suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
USB
- USB 设计（包括一个参考设计，和标准U盘）-USB design (including a reference design, and standards for U disk)
USB2.0FPGAEXAMPLES
- 用于USB20芯片CY7C68013和FPGA之间的通信-comunication between USB and FPGA
2004-02-29_USB_Das_Control_System_dip
- USB的驱动程序 可以方便的使用 已经通过验证-USB driver can easily use has been validated
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
High_Speed_Stream_ADC
- This project attempts to stream high-speed ADC (or other digital) samples into a computer equipped with USB 2.0 CY3681FX2 AD9245
USBblaster
- FPGA的USB应用电路，已经成功通过测试，可以量产。-Application of FPGA circuit of the USB has been successfully tested, can be mass production.
ebook_USB2.0_intel_tranceiver
- High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor
usb_funct
- USB 2.0 verilog源代码,内包含详细文档资料。-USB 2.0 verilog source code, which contains detailed documentation.
CPLD_USB
- ：CPLD 可编程技术具有功能集成度高、设计灵活、开发周期短、成本低等特 点。介绍基于ATMEL 公司的CPLD 芯片ATF1508AS 设计的串并转换和高速 USB 及其在高速高精度数据采集系统中的应用-: CPLD programmable technology with a high degree of functional integration, design flexibility, short development cycle, and low cost. ATMEL-b
usb_phy_verilog.tar
- usb的逻辑设计代码，供大家研究或使用，参考-the logic design usb code, or use for your research, reference
usb_funct
- usb 2.1 IP 的 东西 很好的 是 我的 -usb2.1 IP it s so eay to me to you
usb_funct
- USB接口开发的源代码,包括软件和硬件，学习USB非常好用的资料-USB interface, the development of source code, including software and hardware, learning is very easy to use USB data
xps_usb2_device
- it said to usb module on Xilinx board
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code