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uartok
- 采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
rec
- uart串口通信程序 用VERILOG HDL 编写 可以有效应用于FPGA上
FPGA与USB通信的测试代码
- FPGA与USB通信的测试代码，包括FPGA中的程序（Verilog编写）和PC机上的主控程序以及USB固件程序。,FPGA and the USB communication test code, including the FPGA in the procedure [Verilog prepared] and PC-control procedures, as well as the USB firmware.
asfifodesign
- 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
UART
- 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
RS232(verilog)
- 串口RS232通信程序，包括对串口通信原理的说明。-RS232 serial communication program, including a descr iption of the principles of serial communication.
usbFPGAconnect
- 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, incl
PCMverilog
- 实现了数字通信系统中PCM编码，用Verilog硬件描述语言编程在FPGA上实现的。-Achieved in the PCM coded digital communication system, using Verilog hardware descr iption language programming implemented on the FPGA.
fsk
- 数字通信中的FSK调制解调的原理和过程, 通过用Matlab 对这一过程的编程,分析信号在理想信道和加噪信道中传输时的时域图, 并用蒙特卡罗算法进行仿真。-Digital communications in FSK modulation and demodulation principle and process, through the use of Matlab in the process of programming, analysis of signals in the ideal c
uart
- verilog写的与电脑通信的uart，我实验过了，一切都很好，工作很好-verilog written communication and computer uart, I had the experiment, everything is very good, very good work
8B10B
- 8B10B编解码的较为详细的介绍，8B10B是目前的很多通信网络采用的编解码标准。-8B10B encoding and decoding of a more detailed introduction.
Receiver
- OFDM通信系统接收端完整verilog代码-OFDM communication system receiver complete verilog code
Transmitter
- OFDM通信系统发送端完整verilog代码-OFDM communication system transmitter complete verilog code
code
- <基于Verilog HDL的通信系统设计>源码，包含ASK,FSK,PSK,QPSK,PPM等的调制解调-< Verilog HDL-based communication system design> source, including ASK, FSK, PSK, QPSK, PPM and other modem
FPGA_serial(verilog)
- 采用verilog语言编写的关于串口通信的程序，可以参考，希望有所帮助。-Verilog language on the serial communication program can help.
CH04_GTP_TEST
- GTP IP核，高速通信必须学习的部分。(GTP IP kernel, part of high-speed communication that must be learned.)
uart
- 一个具有固定波特率的 UART 串口收发器，可以实现 串口收发器，可以实现 9600 波特率的串口通信， 能够与 PC 机串口进行通信，支持 8 比特数据位、 1 比特停止位、无校验硬件流控模式(A fixed baud rate UART serial transceiver, can realize serial transceiver, can achieve 9600 baud rate serial communication, and can communicate with PC
eetop.cn_串口Verilog程序(已验证)
- 基于Verilog编写的串口通信协议模块(Serial communication protocol module based on Verilog)
fpga 实现 串口通信
- 串口通信，可以任意修改波特率， 亲自验证过，通信可靠，采用verilog HDL语言编写，代码包含注解