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iic
- iic 总线 verilog 源代码 标准i2c总线， 有sda scl 时钟，频率自定
16QAM_verilog 使用Verilog实现全数字的16QAM调制器
- 使用Verilog实现全数字的16QAM调制器，假设载波的频率为1MHz，数据比特率为100kbit/s.包括源代码和testbench-use verilog to realize 16qam,carrier frequency is 1MHz,data rate is 100kbit/s.including source code and testbench
Sampling_Frequency_Synchronization
- 802.11a接收机的采样频率同步源码，verilog语言的-802.11a receiver sampling frequency synchronization source, verilog language
verilog_16QAM
- 使用verilog实现全数字16QAM调制器，载波频率1MHZ，数据比特流的速率为100Kbps,-the modulation of 16QAM based on FPGA
DDFS_verilog
- 直接数字频率综合器，采用ROM压缩法，经过FPGA验证和AISC实现-Direct digital frequency synthesizer, using ROM compression method, validation and AISC through FPGA Implementation