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up_buhuo
- 这是一个VERILOG接收端捕获模块，扩频码32倍，可以检测到相关峰-This is a VERILOG receiver capture module ,the spreader is 32,it can test the correlation peak
code_gen2
- GPS中C/A码生成电路，用于ＧＰＳ接收机中的跟踪和捕获。-GPS in the C/A code generating circuit for the GPS receiver to track and capture.
UART_RX
- receiver data from computer via com-interface.
A.Software.Defined.GPS.and.Galileo.Receiver
- Software-defined radios (SDRs) have been around for more than a decade. The first complete Global Positioning System (GPS) implementation was described by Dennis Akos in 1997. Since then several research groups have presented their contribution
Receiver
- This file recieves the serial data from the UART and forward to Serial To Parallel module
RAKE_Receiver
- rake receiver thesis
communication
- QAM Radio in Matlab. Software defined radio with transmitter and receiver simulated in Matlab. 16-QAM.
Channel_Equalizer
- 802.11a接收机的信道均衡源码，verilog语言的-802.11a receiver channel equalizer source, verilog language
FMreceiver
- FM receiver VHDL code
all_digital_fm_receiver_latest
- Fm receiver using DP-Fm receiver using DPLL
vhdl_serial_transmitter
- a good serial transmitter in vhdl , there is also receiver code along with this , check it in same web
FPGA_UART
- 本例用VHDL语言在FPGA上实现UART的控制，包括了波特率发生器，接收器，发送器，奇偶校验模块，以及滤波模块和测试模块，能让您更透彻的了解UART的工作原理。-In this case the FPGA using VHDL language to achieve UART' s control, including the baud rate generator, receiver, transmitter, parity modules, and filtering module
Receiver
- OFDM通信系统接收端完整verilog代码-OFDM communication system receiver complete verilog code
gps
- about gps receiver design
fulltext01
- System Design of RF Receiver and Digital Implementation of Control Logic