uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b

I2C总线是一种非常常用的串行总线，它操作简便，占用接口少。本程序(verilog hdl)介绍操作一个I2C总线接口的EEPROM AT24C02 的方法，使用户了解I2C总线协议和读写方法。-The I2C bus is a very common serial bus, it is simple, occupy less interface. This program (verilog HDL) introduced operating a AT24C02 EEPROM of I2C

VHDL 语言实现的串转并 SPI 等等 实现-The SPI bus is a 3 wire bus that in effect links a serial shift-- register between the master and the slave . Typically both the-- master and slave have an 8 bit shift register so the combined-- register is 16 bits. Whe