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uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
UART
- 本人自己编写的FPGA异步串口通信模块(UART),基于QuartusII环境,verilog语言编写,包含仿真和全部程序及说明,验证通过,具有很好的稳定性和参考价值!-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
FPGA_UART
- 本例用VHDL语言在FPGA上实现UART的控制,包括了波特率发生器,接收器,发送器,奇偶校验模块,以及滤波模块和测试模块,能让您更透彻的了解UART的工作原理。-In this case the FPGA using VHDL language to achieve UART' s control, including the baud rate generator, receiver, transmitter, parity modules, and filtering module
RS232
- simple example for uart on fpga
uart
- Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
UART_VHDLCodes
- 基于VHDL的异步串口收发器,在FPGA上设计Uart接收模块实现从pc接收串口数据; 在FPGA上设计Uart发送模块,把从pc接收的数据的16进制值加1再发送给PC; 设计单片机和FPGA接口模块,把接收到的数据送给单片机,并显示在LCD上 -VHDL-based asynchronous serial transceivers Uart receive module in the FPGA design from pc to receive serial data desig
用FPGA实现UART
- 用fpga实现异步串行通信。通过串口助手接收与发送(Implementation of serial communication with FPGA)