简化LAPS协议实现,包括系统设计，FCS处理,对LAPS设计进行验证，说明了设计的正确性。给出了仿真波形，附代码和文档说明。-Simplify the LAPS protocol implementation, including system design, FCS treatment, verification of LAPS design shows that the design is correct. Gives the simulation waveforms, with a co

并行DA和AD转换，能够成功实现其功能。已在FPGA开发板上验证。实现较高的数据转换精度。-Parallel DA and AD conversion, to successfully achieve its function. FPGA development board has been verified. Achieve higher precision data conversion.

FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1

用于FPGA的按键消抖的Verilog文件，经过modelsim仿真和下板验证。-Verilog file for FPGA key debounce, after modelsim simulation and verification under the plate.