FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1

用于FPGA的按键消抖的Verilog文件，经过modelsim仿真和下板验证。-Verilog file for FPGA key debounce, after modelsim simulation and verification under the plate.