serial port rs232 in verilog source code

用VHDL和Verilog语言编写的总线的源程序，从开源网站上下载下的，希望对大家有用-Using VHDL and Verilog source code written in the bus, from the open-source Web site to download the next, and hope for all of us

一种简单的FIFO的verilog代码，有利于理解FIFO的工作原理-code of fifo in verilog