搜索资源列表
vga
- 基于FPGA的VGA时序产生/控制器，产生行、场同步时序，并以标准格式输出,并有相应测试代码。开发工具ISE 8.1及以上。-FPGA-based VGA timing generator/controller, resulting in horizontal and vertical sync timing, and a standard format output, and the corresponding test code. Development tool ISE 8.1 and a
hardh264
- 一个硬件H264编码的VHDL源码，用于FPGA开发，适合IP摄像头等视频设备输出数据的编码。用Xilinx工具测试过，但代码不只是用于Xilinx。-A hardware h264 video encoder written in VHDL suited to IP cameras and megapixel cameras. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools
video_controller
- 可用于FPGA的IP核，适用视频控制领域。-FPGA can be used for the IP core, the application of video control.
my_audio
- 很详细的关于FPGA视频方面的VHDL程序-Very detailed video on the FPGA area VHDL program ..
PitchMarker.m
- This the pitch marker to be used with the PSOLA algorithm for pitch shifting-This is the pitch marker to be used with the PSOLA algorithm for pitch shifting
CAVLC
- H.264 CAVLC硬體原始碼下載，內附測試檔案。-H.264 CAVLC Hardware Verilog source code
mp4format
- MP4文件格式说明，方便你了解MP4的文件格式。-MP4 file format descr iption, allowing you to understand MP4 file format.
4
- 采用现场可编程门阵列FPGA实现大部分外围电路，大大提高了数据采集和处理能力-Use of field programmable gate array FPGA to achieve most of the external circuit, greatly improving the data acquisition and processing capabilities
FPGA_MPEG2TS
- 基于FPGA的MPEG2TS码流实时分析与检测系统,用于学习FPGA的实例说明文档-FPGA_MPEG2TS
3S50AN_configs
- 经典FPGA芯片3S50AN相关资料，配置文件相关的东西，有用的朋友下吧-Classical FPGA chip 3S50AN information, configuration files related stuff, useful friend, are you
04_PlanAhead
- planahead fpga 设计视频介绍-4-planahead fpga design demo-4
DE2_70_i2sound
- 非常好的源代码文件 已经在fpga开发板上验证-Very good source code files in fpga development board to verify
VGA-standrad
- 详细介绍了VGA各个分辨率各帧频的时序标准，在FPGA编程过程中有重要作用-Details the various resolution and frame rate of the VGA timing standards, an important role in the FPGA programming process
CD1_OV5620_SAVE_UDP_TRANS
- OV5620 VHDL CODE, Alter FPGA Source Code.
nios-vedio
- nios2视频教程，开发FPGA软核的资料-Nios2 video tutorial, the development of FPGA soft core data
Face_Detect
- 基于FPGA的视频中的人脸检测算法，亲测可用-FPGA video face detection algorithm, pro-test available
Triple-Rate---DualLink-FPGA-IP-v-2.0-Jul-2008
- Parallel to 5 pair HDSDI encode/decode
PRNG
- 基于FPGA伪随机序列产生器，GOLLMANN级联F-FCSR，产生伪随机序列-FPGA-based pseudo-random sequence generator, GOLLMANN cascade F-FCSR, generating pseudo-random sequence
ROM-MIF
- 利用MATLAB产生FPGA IP 核ROM，初始化文件，用来初始化ROM的MIF文件-Using MATLAB generates FPGA IP Core ROM, initialization files, MIF file is used to initialize the ROM