搜索资源列表
sadct
- adi 汇编写的2维FDCT程序,分成两个1D-DCT,每个1D-DCT 使用12次乘法和32次加法-Sa'adi compilation of the two-dimensional writing FDCT procedures, divided into two 1D - DCT. Each one D-12 DCT use multiplication and 32 Adder
vhdl3
- 2 programs including half adder.
adder
- 基于vhdl硬件描述语言的8位加法器的设计-Based on the design of the 8-bit adder VHDL hardware descr iption language
VD1
- VHDL code of full adder
csa_16
- The folder contains the carry adder code in vhdl. 16 bit adder is designed and coded in vhdl-The folder contains the carry adder code in vhdl. 16 bit adder is designed and coded in vhdl
jiajiajia
- VB加法器，可以进行加法运算，支持科学计数法以及小数等等。而已成为偷懒的好工具！-VB adder, addition operations can support scientific notation and decimal and so on. Only be a good tool for lazy!