搜索资源列表
quartus-mult
- mult,在quartusII中,以模块输入形式,仿真乘法器mult,得到时序图和功能图-a simulation example of mult
develop_frame_find
- 基于FPGA中OFDM中的帧检测,由于采用简化算法,采用较少的复数乘法器,易于硬件实现,且节省资源,采用verilog实现.-Frame detection based on FPGA for OFDM, a simplified algorithm, using less complex multiplier, easily implemented in hardware, and save resources, the SNR performance is slightly lower th
LIA
- 该vhdl代码用两个rom模拟产生两路正弦波,并设计了一个乘法器将两路正弦波相乘。-The two vhdl code with two rom analog sine wave and design a multiplier to multiply two sine wave.
MULT
- 用VERILOG实现乘法器功能,通过仿真验证-With VERILOG multiplier function is verified by simulation
lbq3
- 滤波器的verilog代码 主要是对算法的折叠 有原先的4个加法器四个乘法器变成2个加法器两个乘法器-Filter verilog code folding algorithm 4 adder four multipliers into two adders and two multipliers
booth_multiplier
- 从google上下载到的booth乘法器-booth multiplier
Verilog_divid
- vhdl语言描述传统除法器,传统乘法器的改进,从原理到实现的传统除法器-vhdl language to describe the traditional divider, the improvement of traditional multiplier principle to achieve the traditional divider
mux16
- 16位乘法器的verilog实现,可以通过仿真,采用的是移位的方法。-16-bit multiplier verilog achieve, through simulation, using the shift method.
Mul32
- Verilog语言编写的单精度浮点数乘法器-The Verilog language of single precision floating point multiplier
multiplier-experiment
- 周立功Fusion StartKit,fpga开发板的实验例程,恒定系数乘法器实验-The ZLG Fusion StartKit, fpga development board test routines, the constant coefficient multiplier experiment
mulbinarytree
- 16位二叉树乘法器(阵列乘法器),VHDL实现-16-bit binary tree multiplier (array multiplier), VHDL realization
xiangwei_90
- 产生一组正交的载波信号,应用于斩波相乘控制,模拟乘法器-Generating a set of orthogonal carrier signals, multiplied by the applied chopper control, analog multiplier. . .
mul
- CCS环境下,在DSP硬件板上实现矩阵乘法器。-CCS environment matrix multiplier in DSP hardware board.
8mutip
- verilog 八位 乘法器-verilog eight multiplier
costasc_verilog
- 实现costas环,用verilog语言实现,缺少乘法器,可以自己添加-Realization of Costas ring, with the Verilog language implementation, the lack of multiplier, you can add their own.
DDC_FPGA
- 基于FPGA的数字下变频器(DDC)的设计,将采样得到的高速率信号变成低速率基带信号,以便进行下一步的信号处理。由NCO、数字混频器、低通滤波器和抽取滤波器四个模块组成。采用自编的加法树乘法器,提高乘法运算效率。-Design based on FPGA digital downconverter (DDC), the high-speed signal will be sampled baseband signal into a low rate for the next step in th
mult4x4
- 4*4乘法器的源代码,利用FPGA的查找表实现,是数字电路和FPGA的经典乘法器源代码-4* 4 multiplier source code, FPGA lookup table to achieve classic digital circuit and FPGA multiplier source code
FPGA-multiplier-on-chip
- 典型实例11.5 FPGA片上硬件乘法器的使用 软件开发环境:ISE 7.1i 硬件开发环境:红色飓风II代-Xilinx版 本实例实现一个IIR滤波器,并在ISE里面进行仿真。 \rtl目录里面是源文件 \project目录里面是工程-Typical examples 11.5 FPGA chip hardware multiplier using the software development environment: ISE 7.1i hardware d
ade
- 用verilog HDL语言实现一个8位串行乘法器-An 8-bit serial multiplier with Verilog HDL language
mul_addtree
- 用verilog HDL语言实现一个4位的流水线乘法器-Achieve a 4-bit pipelined multiplier using Verilog HDL language