搜索资源列表
5-6
- 用verilog实现节省乘法器的16位复数乘法-16-bit complex multiplication verilog to achieve savings multiplier
multi_CX
- 实现8*8串行乘法器的verilog源代码,经过调试的哦!-8* 8 serial multiplier verilog source code, after debugging Oh!
multi_4bits_pipelining
- 实现4*4流水线乘法器的verilog源代码,在FPGA板上运行-4* 4 pipelined multiplier verilog source code, running on the FPGA board
mul
- 带符号数的乘法器,包含补码与原码之间的转换-failed to translate
multiplier_ip
- 基于IP核的乘法器设计,完整的设计工程文件在multiplier_ip文件夹下-IP-based core multiplier design, complete design engineering file multiplier_ip file folder
multiply_shift_add
- 基于移位相加运算的乘法器设计,完整的设计工程文件在multiply_shift_add文件夹下-Multiplier design based on shift and add operations, complete design engineering file multiply_shift_add file folder
Chapter16-Multiplier
- 书籍《精通Verilog HDL语言编程》中第16章的程序实例代码,是关于常用乘法器的设计的,对于初学者有一定的帮助-Book "Proficient in Verilog HDL language programming" in Chapter 16 of the procedure code, the common multiplier designed for beginners will certainly help
16-bit-parallel-mult
- 16位并行乘法器, 由四个4位乘法器组成-16-bit parallel multiplier, consisting of four four multipliers
VHDL_book2
- add4a:4位加法器的设计 add8a:8位加法器的设计 subtract:4位减法器的设计 addsub: 4位加法器/减法器的设计 shift4:移位寄存器的设计 mult4:乘法器设计 div8:除法器设计 alu4:算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtraction Design addsub: 4-bit ad
16bits_multiplier
- 这是一个有符号的16位乘法器的设计,包含详细的设计报告和全部的verilog代码。乘法器采用booth编码,4-2压缩,超前进位结构-This is a signed 16-bit multiplier design, detailed design reports and contains all of the verilog code. Multiplier using booth encoding ,4-2 compression, lookahead structure
module-multiplier
- 用vhdl编程,实现了一个2^N+1模乘法器,经验证,设计结果完全正确-use the vhdl language to design a module 2^n+1 multiplier
EX4
- 基于FPGA的16位乘法器,入门的可以好好看看。-FPGA-based 16-bit multiplier, getting started can be a good look.
chengfaqi
- 通过verilog hdl语言实现伽罗华域GF(q)乘法器设计-By verilog hdl language Galois field GF (q) Multiplier
SUANSHUJISUAN
- 通过verilog hdl实现加法器乘法器,除法器的设计-Achieved through verilog hdl adder multiplier, divider design
VHDL-
- 8位相等比较器,布斯乘法器,以为寄存器的VHDL实现-Eight for phase comparator, Booth multiplier, that registers of VHDL
multiplying-unit
- FPGA/CPLD开发,基于VHDL语言的乘法器的实现,数码管显示-FPGA/CPLD development, based on the realization of VHDL language multipliers, digital display
booth-16_16-multiplier
- 由verilog编写的利用booth编码的16*16有符号乘法器的代码,没有pipeline-a 16*16 multiplier with booth coding by verilog
verilog-codes-for-booth2
- 由verilog编写的采用booth2编码的16*16乘法器-a 16*16 multiplier with booth2 coding by verilog
chengfaqi
- 基于fpga的乘法器设计 已经验证请放心下载-Fpga-based multiplier design has been verified, please rest assured download
Ex3_4
- 两个16位整数相乘,乘积总是“向左增长”,这意味着多次相乘后乘积将会很快超出定点器件的数据范围。而且要将32位乘积保存到数据存储器,就要开销2个机器周期以及2个字的程序和RAM单元;并且,由于乘法器都是16位相乘,因此很难在后续的递推运算中,将32位乘积作为乘法器的输入。然而,小数相乘,乘积总是“向右增长”,这就使得超出定点器件数据范围的是我们不太感兴趣的部分。在小数乘法下,既可以存储32位乘积,也可以存储高16位乘积,这就允许用较少的资源保存结果,也便于用于递推运算中。这就是为什么定点DSP芯