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mux16
- 十六位乘法器的verilog hdl 实现 及 modelsim 仿真 环境为quartusii9.0 自动调用modelsim 6.5输出仿真结果-fpga verilog hdl modelsim quartusii 16-bit multiplier
mux4booth
- fpga 使用verilog hdl 语言，quartusii 9.0编程环境，使用2booth算法设计的4bit乘法器。可以扩展为16bit乘法器。-fpga verilog hdl ，quartusii 9.0 ，2booth 4bit
multt
- 该程序实现了一个16*16的乘法器，可以用作设计乘法器参考-The program implements a 16* 16 multiplier, multiplier design can be used as reference
MSP430F5438_example
- MSP430F5430例程,包括AD采集模块、时钟模块、乘法器、定时器、串口、看门狗等模块底层驱动源码 -MSP430F5430 routines, including driver source code of AD collection module, clock module, multiplier, timer, serial port, and watchdog module etc.
leijiaqi
- verilog 语言描述的累加器和乘法器-verilog code
Hardware_Multiplier
- 利用MSP430F149内部的硬件乘法器进行8bit-8bit，16bit-16bit的乘法，只需三个主时钟周期，即可读出运算结果。-Using MSP430F149 internal hardware multiplier for 8bit-8bit, 16bit-16bit multiplication, just three master clock cycles, you can read out the result of the operation.
N-bits-by-M-bits
- 这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器-This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier
ARITHMETIC
- 算术乘法器，这是我自己设计的算术乘法器，是用VHDL语言设计的，希望对大家有帮助-Arithmetic multiplier, this is my own design arithmetic multiplier, is designed with VHDL language, and they hope to help everyone
multiplier
- 乘法器的verilog工程文件，可以进行仿真实验，有详细解释，适合初学者学习参考。-Multiplier verilog project file, can be simulated, with detailed explanations, suitable for beginners to learn.
mux16
- 在该实验中就是要利用时序逻辑设计方法来设计一个16 位乘法器-In this experiment is to use sequential logic design method to design a 16-bit multiplier
HighSpeedParallelMultiple
- quartus II 下VHDL实现快速乘法器-quartus II VHDL High Speed Parallel Multiple
mult
- verilog编写的8x16常变量乘法器，可用quartus仿真-verilog prepared 8x16 often variable multiplier, available quartus simulation
A-C8V4
- 淘宝畅销FPGA开发板的A-C8V4 电路图及例子 9实验九：利用语言实现3-8译码器 10实验十：利用语言实现按键和数码管显示 11实验十一：利用语言实现乘法器数码管显示 …… 18实验十八：利用语言实现蜂鸣器唱歌 23实验二十三：利用语言实现LCD1602显示 24实验二十四：利用语言实现LCD12864显示汉字 25实验二十五：利用程序实现串口RS232与电脑通信 28实验二十八：利用程序实现VGA显示RGB彩条信号 31实验三十一：利用程序实
mux16
- 利用FPGA时序逻辑设计16位乘法器。利用时序逻辑设计可以使整体设计具备流水线结构-Sequential logic design using FPGA multiplier 16. Sequential logic design allows the use of the overall design with pipeline structure
FPGA_multiplier
- 本源码是用verilog语言编写的FPGA乘法器，可以输入两个8位数据，出输16位结果。-The source code is written in verilog FPGA multiplier, you can enter two 8-bit data, the output 16 results.
16_bit
- 采用boot算法的16位乘法器,速度较快，可以试下哈-Boot algorithm using 16-bit multiplier, faster, you can try under the Kazakhstan
Common-multiplier-design
- 常用乘法器设计，用FPGA能实现，值得下载。-Common multiplier design, FPGA can achieve, it is worth downloading.
GF-(q)-multiplier-design
- 伽罗华域GF（q）乘法器设计,FPGA实现-Galois field GF (q) multiplier design, FPGA realization
method1
- 脉动乘法器的HDL实现，包括DC、Astro跑版图-using HDL implements GM multiplier，including src，DC，and Adtro layout
altfp_mult_abs
- 浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly