伪随机二进制序列发生器的Verilog源码，带测试文件，并在FPGA开发板上成功验证-Pseudo-random binary sequence generator Verilog source code, with a test file, and successfully verified in FPGA development board

基于verilog产生伪随机二进制序列，序列速率为5M(A pseudo-random binary sequence based on verilog.)