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paobiao
- 一个基于FPGA的数字跑表系统的设计,最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
juzhenjianpan
- 本源码用VHDL语言实现了用键盘控制米字管显示十进制-VHDL
eight_decimal
- 用VERILOG写的8位十进制频率计 注释非常清晰 有助菜鸟学习-VERILOG written with eight decimal Notes Cymometer help rookie learning very clear
MCS50-ASM3
- MCS51-ASM 单片机源码系列之 第三章 十进制(BCD码)数运算-MCS51-ASM-source series of single-chip Chapter decimal (BCD code) the number of computing
count10
- 基于Quartus II的十进制加法计数器的项目设计,包含了项目文件和VHDL源代码-Quartus II based on the decimal adder counter the project design, including project documents and VHDL source code
cd4000x
- CD4000 双3输入端或非门+单非门 TI CD4001 四2输入端或非门 HIT/NSC/TI/GOL 双4输入端或非门 NSC CD4006 18位串入/串出移位寄存器 NSC CD4007 双互补对加反相器 NSC CD4008 4位超前进位全加器 NSC CD4009 六反相缓冲/变换器 NSC CD4010 六同相缓冲/变换器 NSC CD4011 四2输入端与非门 HIT/TI CD4012 双4输入端与非门
Cymometer_of_four_decimal
- 四位十进制数字频率计: 测量范围:1Hz~10kHz; 显示时间不少于1S; 具有记忆显示的功能,即在测量过程中 刷新数据,等结束后才显示测量结果,给出待测信号的频率值,并保存到下一次测量结束。-Four decimal digital frequency meter: measuring range: 1Hz ~ 10kHz show that no less than 1S with memory function showed that the cour
18B20ceiwen
- 本程序实现了基于C8051F020和DS18B20温度传感器的温度测量并在数码管上以十进制形式显示-This procedure based on the C8051F020 and the realization of DS18B20 temperature sensor and temperature measurement in the digital control on the form to the metric system
21
- 1数据传送与多字节十进制加法实验 1. 数据传送实验 把数据0A0H放到地址为40H内存单元,并将数值和地址分别递增1,要求一共做十次这样的操作。 将内存空间40H-49H的数值分别传递给50H-59H的内存空间中 2. 多字节十进制加法实验 将存放在单片机内部RAM中以40H为首的3个地址单元中的一十进制数与存放在50H为首的3个地址单元中的一十进制数相加,将相加结果存放在以60H为首的地址RAM地址单元中。 2要求在8个LED数码管显示8
chenggong
- 实现由一个4位十进制数码管(含小数点)显示结果,其测量范围为1Hz~9999KHz,能自动根据7位十进制的结果,自动选择有效数据的高4位进行动态显示(即量程自动转换),小数点表示是千位,即KHz,-To achieve a 4 decimal digits (including decimal point) shows the results of its measurement range of 1Hz ~ 9999KHz, automatically in accordance with t
counter
- 这是用VHDL设计的十进制计数器,两个VHDL程序分别说明了out和buffer的区别-It is designed with VHDL decimal counter, the two VHDL procedures were illustrated the difference between out and buffer
vaa
- (1)设计一个4位十进制的频率计其测量范围1Hz~9.999KHz;6 N3 G8 k( U- @ n* A (2)记数过程结束后,保存并显示结果;-(1) to design a metric four of its frequency range 1Hz ~ 9.999KHz 6 N3 G8 k (U-@ ' n* A (2) After the counting process, preserve and display the results
aa
- 一﹑指标要求:. A: f5 b G A( d8 n (1)设计一个4位十进制的频率计其测量范围1Hz~9.999KHz;6 N3 G8 k( U- @ n* A (2)记数过程结束后,保存并显示结果;-﹑ Indicators a request:. A: f5 b G A (d8 n (1) to design a metric four of its frequency range 1Hz ~ 9.999KHz 6 N3 G8 k (U-@ ' n* A (2
jishuqi8421
- 用VHDL语言实现8421码的十进制计数器,状态变化0000->0001->0010->0011->0100->0101->0110->0111->1000->0000.循环往复。 -VHDL language with 8421 yards of the decimal counter, a state of change 0000-> 0001-> 0010-> 0011-> 0100-> 0101-&g
shijinzhi
- 利用FPGA做出十进制加减法!带有进位借位显示-FPGA to make use of the decimal addition and subtraction! By a binary digital display
Quartus32
- 1.8421码十进制计数器 2.分频系数为8,占空比为0.5的分频器 3.控制8个二极管的电路-Counter 2 decimal 1.8421 yards. Sub-frequency coefficient of 8, duty cycle of the divider 3 for the 0.5. 8 diode control circuit
seven_segment
- 用veirlog写成的七段显示器 可以把十进制转成七段显示器上面的显示数字-Paragraph written by veirlog display can display the metric system into the above paragraph shows that the number of
dig_scan
- 将AD采样的八位比特转化为十进制数值大小,并用数码管动态显示-The AD sample into the eight-bit decimal numerical size, and dynamic display with digital control
counter1
- 带复位和时钟使能的十进制计数器 verilo 描述-With reset and clock enable verilo descr iption of the decimal counter
counter
- 利用EDA工具MAX-PlusII的VDHL输入法,输入VHDL程序,实现2位计数器,在七段译码器上以十进制显示:0、1、2、3、0、...。时钟信号使用83管脚。采用自动机状态转换方式设计该计数器;建立相应仿真波形文件,并进行波形仿真;分析设计电路的正确性。-The use of EDA tools VDHL of the MAX-PlusII input method, enter the VHDL program, the realization of two counters, in t